INDUCTORLESS SELF-TUNED INPUT-MATCHING LOW-NOISE AMPLIFIER WITH VERY LOW NOISE FIGURE AND Gm BOOST

ABSTRACT

A low-noise amplifier is disclosed having a first transistor with a first current terminal coupled to a supply voltage rail through a load resistor and a second current terminal coupled to an input node, wherein a bias resistor is coupled between the input node and a fixed voltage node. A second transistor has a third current terminal coupled to an output node and a fourth current terminal coupled to the fixed voltage node. A feedback capacitor is coupled between the input node and the output node, wherein capacitance of the feedback capacitor is sized to eliminate the need for coupling an input impedance matching inductor to the input node.

RELATED APPLICATIONS

This application claims the benefit of provisional patent applicationSer. No. 63/375,064, filed Sep. 9, 2022, and claims the benefit ofprovisional patent application Ser. No. 63/400,502, filed Aug. 24, 2022,and claims the benefit of provisional patent application Ser. No.63/342,678, filed May 17, 2022, the disclosures of which are herebyincorporated herein by reference in their entireties.

This application is related to U.S. patent application serial number______, titled LOW NOISE AMPLIFIER (LNA) WITH DISTORTION AND NOISECANCELLATION and filed concurrently, which claims the benefit ofprovisional patent application Ser. No. 63/375,064, filed Aug. 9, 2022,and claims the benefit of provisional patent application Ser. No.63/342,678, filed May 17, 2022, the disclosures of which are herebyincorporated herein by reference in their entireties.

FIELD OF THE DISCLOSURE

The technology of the present disclosure relates to a low-noiseamplifier structure without an input impedance matching inductor.

BACKGROUND

A low-noise amplifier (LNA) is a key block for a receive chain since itdetermines the sensitivity of the receiver. Assuming that enough gain isprovided by the LNA, the noise contribution of the next stages can besignificantly reduced at the input of the receiver. The input impedanceof the LNA usually is conjugately matched with the source impedance toreceive the maximum input power. On the other hand, the optimum sourceimpedance to reach minimum noise figure is different from the actualsource impedance, which causes trade-offs between input matching andachievable minimum noise figure. The LNAs in general are divided intonarrow band and wideband amplifiers. The narrow band LNAs achieve alower noise figure compared with wideband LNAs. On the other hand,unlike wideband LNAs, narrow band LNAs require off-chip matchingcomponents that make them less attractive for low-cost applications. Theother key performance parameter of the LNA is the in-band andout-of-band linearity, which can be specified as second-order andthird-order input-referred intercept points (IIP2 and IIP3) or a 1 dBsaturation point. However, the linearity of the receive chain isdetermined mostly by the next stages of the LNA, and a highly nonlinearLNA can be saturated by lower input power levels. Therefore, to preventearlier saturation of LNA output, the maximum gain of the LNA should bereduced, which subsequently increases the noise contribution of the nextstages. The 4G/5G front-end modules employ multi-input LNA cores forintended bands for carrier aggregation and multiple input, multipleoutput functionality. Therefore, it is desirable that all the noisefigure, input matching, and linearity requirements of a LNA are metwithout using any off-chip components to keep the integration cost lowand to reduce occupied area within the module, which makes shrinking thesize of the module possible.

SUMMARY

A low-noise amplifier (LNA) is disclosed having a first transistor witha first current terminal coupled to a supply voltage rail through a loadresistor and a second current terminal coupled to an input node, whereina bias resistor is coupled between the input node and a fixed voltagenode. A second transistor has a third current terminal coupled to afeedback output node, and a fourth current terminal is coupled to thefixed voltage node. A feedback capacitor is coupled between a gate ofthe first transistor and the feedback output node, wherein capacitanceof the feedback capacitor is sized to eliminate the need for coupling aninput impedance matching inductor to the input node and meanwhile reducethe noise figure of the LNA.

In exemplary embodiments, the disclosed LNA is a self-tunableinput-matching LNA for mid-high band 4G/5G front-end module applicationsachieving very low noise figure (NF<1 dB) and high gain (>20 dB). Theneed for an inductor-based input-matching network at the input node ofthe LNA is eliminated. The disclosed LNA is a wideband LNA that is madeup of a common-gate (CG) stage that is configured as a widebandinput-matching amplifier and a common-source (CS) amplifier to cancelthe channel noise of the CG device at output. The disclosure providesfor a transconductance (gm) boosting technique (a) to suppressconsiderably the significant noise contribution of the bias and loadresistors of CG amplifier so that NF<1 dB can be achieved and (b) toautomatically match the input resistance as the output tank is tunedwithout using any off-chip component. In addition to inherent distortioncancellation, selectivity characteristic of input return loss improvesout-of-band linearity. By employing the device according to the presentdisclosure for designing a multi-core LNA die, the integration costwithin a front-end module can be reduced considerably and a very low NFcan be achieved.

In another aspect, any of the foregoing aspects individually ortogether, and/or various separate aspects and features as describedherein, may be combined for additional advantage. Any of the variousfeatures and elements as disclosed herein may be combined with one ormore other disclosed features and elements unless indicated to thecontrary herein.

Those skilled in the art will appreciate the scope of the presentdisclosure and realize additional aspects thereof after reading thefollowing detailed description of the preferred embodiments inassociation with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part ofthis specification illustrate several aspects of the disclosure and,together with the description, serve to explain the principles of thedisclosure.

FIG. 1 is a schematic of a wideband differential output low-noiseamplifier (LNA) with noise cancellation (bias circuit is not shown).

FIG. 2 is a schematic of a wideband single-ended LNA with noisecancellation (bias circuit is not shown).

FIG. 3 is a schematic of a self-tuned input-matching LNA with reducednoise contribution of a load resistor and a bias resistor in accordancewith the present disclosure (bias circuit is not shown).

FIG. 4 is a schematic showing another embodiment based on the circuit ofFIG. 3 and using a p-type metal oxide semiconductor as an inverter toreuse the bias current and cancelling harmonics.

FIG. 5A is a graph showing input return loss for the LNA in accordancewith the present disclosure.

FIG. 5B is a graph showing reverse isolation for the LNA in accordancewith the present disclosure.

FIG. 5C is a graph showing gain for the LNA in accordance with thepresent disclosure.

FIG. 5D is a graph showing output return loss for the LNA in accordancewith the present disclosure.

FIG. 6 is a graph showing self-tuned input matching over a frequencyrange of 1.4 GHz to 2.7 GHz for the LNA in accordance with the presentdisclosure.

FIG. 7A is a plot showing noise figure for the LNA in accordance withthe present disclosure.

FIG. 7B is a plot showing the stability factor for the LNA in accordancewith the present disclosure.

FIG. 8A is a graph showing input-referred IP3 with an extraction pointof −30 dBm for the LNA in accordance with the present disclosure.

FIG. 8B is a graph showing input-referred IP2 with two extraction pointsof −15 dBm and −30 dBm for the LNA in accordance with the presentdisclosure.

FIG. 9 is a diagram showing how the disclosed LNA may interact with userelements such as wireless communication devices.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information toenable those skilled in the art to practice the embodiments andillustrate the best mode of practicing the embodiments. Upon reading thefollowing description in light of the accompanying drawing figures,those skilled in the art will understand the concepts of the disclosureand will recognize applications of these concepts not particularlyaddressed herein. It should be understood that these concepts andapplications fall within the scope of the disclosure and theaccompanying claims.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present disclosure. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will be understood that when an element such as a layer, region, orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present.Likewise, it will be understood that when an element such as a layer,region, or substrate is referred to as being “over” or extending “over”another element, it can be directly over or extend directly over theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly over” or extending“directly over” another element, there are no intervening elementspresent. It will also be understood that when an element is referred toas being “connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or“horizontal” or “vertical” may be used herein to describe a relationshipof one element, layer, or region to another element, layer, or region asillustrated in the Figures. It will be understood that these terms andthose discussed above are intended to encompass different orientationsof the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a,” “an,” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes,” and/or “including” when used herein specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to schematicillustrations of embodiments of the disclosure. As such, the actualdimensions of the layers and elements can be different, and variationsfrom the shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are expected. For example, aregion illustrated or described as square or rectangular can haverounded or curved features, and regions shown as straight lines may havesome irregularity. Thus, the regions illustrated in the figures areschematic and their shapes are not intended to illustrate the preciseshape of a region of a device and are not intended to limit the scope ofthe disclosure. Additionally, sizes of structures or regions may beexaggerated relative to other structures or regions for illustrativepurposes and, thus, are provided to illustrate the general structures ofthe present subject matter and may or may not be drawn to scale. Commonelements between figures may be shown herein with common element numbersand may not be subsequently re-described.

The narrow band low-noise amplifier (LNA) is used widely for mobileapplications since it provides a very low noise figure (NF<1 dB) whileconsuming reasonable current. The narrow band input matching is achievedby a series resonator at the input which is composed of off-chipcomponents and the source degenerated inductor. The off-chip matchingnetwork is usually composed of a series inductor (L) and shunt capacitor(C) surface-mount devices that occupy considerable area in front-endmodules and add cost. On the other hand, conventional wideband LNAsmatch over a wide frequency range without using off-chip components butsuffer from a poor noise figure (NF>2 dB), which makes them lessattractive for 4G or 5G front-end modules. Therefore, there ischallenging trade-off between achievable noise figure and the inputmatching requirement. Disclosed is an LNA that addresses this trade-offand introduces a LNA without requiring any off-chip matching components(like a wideband LNA) while reducing the noise figure below 1 dB (like anarrow band LNA).

The schematic of conventional common gate-common source (CG-CS) widebandlow-noise amplifier (LNA) 10 is shown in related art in FIG. 1 . Asdepicted in related art in FIG. 1 , the LNA 10 has a first transistor M₁and a second transistor M₂. A drain of the first transistor M₁ iscoupled to a supply rail V_(DD) through a first resistor R₁, and a drainof the second transistor M₂ is coupled through a second resistor R₂. Thefirst resistor R₁ and the second resistor R₂ may also be referred togenerally as load resistors. A source of the first transistor M₁ iscoupled to a fixed voltage node GND1 through a bias resistor R_(b1).Note that complete bias circuitry is not shown and that drain and sourceterminals may also be commonly referred to as current terminals, whilegates may be referred to as control terminals. A gate of the firsttransistor M₁ is coupled to bias voltage (not shown in FIG. 1 ), whichconfigures the first transistor M₁ as a common gate amplifier. A currentsource I_(bias) represents a bias current that flows to the biasresistor R_(b1) from the source of the first transistor M₁. A source ofthe second transistor M₂ is coupled to the fixed voltage node GND1,which configures the second transistor M₂ as a common source amplifier.The fixed node GND1 is ground in this case.

A gate of the second transistor M₂ is coupled to a first node N1 that isbetween the source of the first transistor M₁ and the bias resistorR_(b1). A radio frequency signal (RF) source V_(in) with a RF sourceresistance R_(s) is coupled across the bias resistor R_(b1). Anamplifier output voltage V_(out) is shown between a second node N2 and athird node N3. The second node includes the drain of the firsttransistor M₁, and the third node N3 includes the drain of the secondtransistor M₂. Channel noise generated by the first transistor M₁ isrepresented by a jagged signal trace, and an RF signal generated by theRF source V_(in) is represented by a sinusoidal signal trace at thefirst node N1. Out of phase amplified channel noise and the RF signalare depicted at the second node N2 and the third node N3, respectively.

Input impedance matching is provided by the first transistor M₁ that iscommon gate configured where R_(s)=1/gm₁. In parallel to the firsttransistor M₂, the second transistor M₂ provides some cancellation ofthe channel noise generated in the first transistor M₁. The channelnoise of the first transistor M₁ is substantially cancelled because thechannel noise appears in phase at the drains of the first transistor M₁and the second transistor M₂, as shown in related art in FIG. 1 , whilethe RF input signal appears in the opposite phase at the outputs.Therefore, noise cancellation occurs under the following conditions:

R _(s) ·gm ₂ ·R ₂ =R ₁  (1)

Assuming that input is matched to R_(s), Equation (1) is simplified to

gm ₂ ·R ₂ =gm ₁ ·R ₁  (2)

which means that if the gain of the first transistor M₁ and the secondtransistor M₂ are the same, taking differentially the outputs at thedrains of the first transistor M₁ and the second transistor M₂ cancelsthe channel noise of first transistor M₁ while the output voltageV_(out) is amplified.

FIG. 2 is a schematic of another version of the related-art amplifier 10that adds a third transistor M₃ that is to invert the output of thefirst transistor M₁ and sum the transconductance of the secondtransistor M₂ and the third transistor M₃ at the third node N3.Moreover, the third transistor M₃ is configured to convert differentialoutput to single-ended output.

As depicted in FIG. 3 , the channel noise can be cancelled if

R _(s) ·gm ₂ =gm ₃ ·R ₁·  (3)

Assuming that input impedance is matched to R_(s), Equation (3) issimplified to

gm ₂ /gm ₃ =gm ₁ ·R ₁  (4)

However, the channel noise of the first transistor M₁ can be cancelled,but the noise contribution from the bias resistor R_(b1) and firstresistor R₁ is substantial, which leads to an increased noise factor(NF) of more than 2 dB.

FIG. 3 is a schematic of an LNA 12 that is structured and configured inaccordance with the present disclosure to substantially improve the NFover the related-art LNA 10 depicted in FIGS. 1 and 2 . In thisexemplary embodiment, a coupling capacitor C_(C1) is coupled between thegate of M₃ and the second node N2. The coupling capacitor C_(C1) makespossible to have individual bias voltage for M₃, which plays animportant role for harmonic cancellation of two concurrent paths (CG andCS). In the exemplary embodiment depicted in FIG. 3 , a second couplingcapacitor C_(C2) is coupled between a source resistor R_(s) and thefirst node N1. A third coupling capacitor C_(C3) is coupled between agate of the second transistor M₂ and the source resistor R_(s) and thesecond coupling capacitor C_(C2), which effectively couples the gate ofthe second transistor M₂ to the first node N1.

In the present disclosure two cascode devices have been employed asfollows. A fourth transistor M₄ in cascode with the second transistor M₂is coupled between the third node N3 and the drain of the secondtransistor M₂. The fourth transistor M₄ improves the gain provided bythe second transistor M₂, which in turn lowers the level of bias currentflowing through the first resistor R₁ and the bias resistor R_(b1). Assuch, the LNA 12 reduces the noise contributions of the first resistorR₁ and the bias resistor R_(b1). A fifth transistor M₅ is coupled incascode with the third transistor M₃ and provides isolation between theoutput at a fourth node N4 and the input of the LNA 12 at the first nodeN1.

The LNA 12 is configured to employ transconductance (gm) enhancementthat allows the first transistor M₁ to operate with lower bias currentwhile providing the required gm for input matching. To enhance the gm ofthe transistor M₁, a feedback capacitor C_(f1) (abbreviated as C_(f) inthe following equations) is coupled between the gate of the firsttransistor M₁ and the third node N3 that is coupled to the drain of thethird transistor M₃. In this exemplary embodiment, the third node N3 maybe referred to as a feedback output node. A capacitance value for thefeedback capacitor C_(f1) is between 100 femtofarads and femtofarads. Insome embodiments, the capacitance value of the feedback capacitor C_(f1)is 250 femtofarads ±20%. In other exemplary embodiments, the capacitancevalue for the feedback capacitor is 250 femtofarads ±10%. The feedbackcapacitor C_(f1) may be a metal-insulator-metal that occupies no morethan around 10×12 micrometers of die real estate. A first optionalresistor R_(f1) shown in dashed line may be coupled parallel withfeedback capacitor C_(f1), and/or a second optional resistor R_(f2),also shown in dashed line, may be added in series with feedbackcapacitor C_(f1) to increase the reverse isolation and improve thestability factor with a trade-off to degraded input matching.Resistances of the first optional resistor R_(f1) and the secondoptional resistor R_(f2) may be optimized to provide the bestperformance considering the trade-off between stability factor andreverse isolation. Since the third node N3 is in the opposite phase ofinput voltage with no need for an additional inverter amplifier, thesource-gate voltage of the first transistor M₁ is increased as follows:

Vsg=(1+A _(v))·v _(in)  (5)

where A_(v) is boosting factor. The boosting factor A_(v) is equal tothe gain from the input to the feedback output node, which is the sum ofthe gain of the stage of the first transistor M₁ followed by theinverter-configured third transistor M₃ and the gain of the stage of thesecond transistor M₂ as follows:

$\begin{matrix}\begin{matrix}{A_{v} = \frac{Rca{s.( {{gm2} + {R{1.g}m{1.g}m3}} )}}{1 - {Rca{s.R}{1.g}m{1.g}m3}}} & {{Cf} \gg {{Cgs}1}}\end{matrix} & (6)\end{matrix}$

where R_(cas) is the impedance seen from the third node N3 to which thesource of the fifth transistor M₅ is coupled. Increased source-gatevoltage is equivalent to enhancing the transconductance, and thegate-source capacitance, with the same boosting factor. Therefore, theinput-matching condition changes to the following:

$\begin{matrix}{R_{in} = {\frac{1}{{( {1 + A_{v}} ).g}m_{1}} = R_{s}}} & (7)\end{matrix}$

Then, the noise of M₁ is cancelled if:

gm ₂ /gm ₃=(1+A _(v))·gm ₁ ·R ₁  (8)

It is worth mentioning that a large boosting factor in this design canbe achieved because of amplification through both the amplifier stage ofthe first transistor M₁ and the amplifier of the second transistor M₂.Therefore, the required transconductance gm₁ of the first transistor M₁for input matching is reduced considerably as large as the boostingfactor, which can be achieved relatively easily by lower bias currentand by preserving substantial gate-source overdrive voltage for betterlinearity performance. On the other hand, lower current flowing throughthe first transistor M₁ releases voltage headroom, which allows largeload and bias resistors such as the first resistor R₁ to be used toreduce the noise contribution.

In the present embodiment, by using two cascode devices, the boostingfactor (A_(v)) can be increased, which further reduces the bias currentof the CG stage and consequently the noise contribution of the load andbias resistor of the CG stage. Using one cascode device or taking thedrain of M₂/source of M₄ as output feedback node only provides smallerboosting factor, which does not lead to considerable noise reduction.For applications for which still higher noise figure is acceptable, onecascode device can be used to preserve more voltage headroom, orM₂/source of M₄ can be taken as the feedback output node.

As depicted in FIG. 4 , a schematic of another embodiment of the LNA hasa positive metal oxide semiconductor (PMOS) transistor instead of anegative metal oxide semiconductor (NMOS) transistor used as an inverter(M₃). This allows bias current of the third transistor M₃ to be re-usedby the second transistor M₂, and therefore a substantial current issaved. Another benefit of this embodiment is the cancelling of harmonicsby using complementary devices. This embodiment can be implemented inadvanced technology nodes where PMOS has similar cut-off frequency asNMOS.

Self-Tuned Input Matching

Since the 4G/5G front-end modules are designed based on the carrieraggregation concept, for each band a dedicated LNA core is used. Asdepicted in FIG. 3 , each dedicated LNA core as represented by the LNA12 has an output tank 14 having a tank inductor Li and a tank capacitorC1. A resonance frequency of the output tank 14 of each LNA core iscentered at the mid-frequency of the band and is matched to 50Ω to drivean external receiver module. In this design a conventional resonator isused as load of the LNA 12 and is matched to 50Ω by a capacitortransformer, made up of a first impedance matching capacitor C₁ and asecond impedance matching capacitor C₂.

An important feature of the disclosed LNA 12 is that the input impedancematching is not wideband but rather is narrow band, which automaticallywithout any additional circuitry is tunable over a wide frequency rangeat the same center frequency of the output tank 14. The input matchingcondition is met if the required gain (A_(v)) to boost gm₁ is obtained.The required gain from input to cascode node (A_(v)) is achieved at theresonance frequency of the output tank since a resistance R_(cas) seenfrom the third node N3 reaches to its maximum value. In other words, theimpedance seen from the third node N3 depends on an impedance Z_(l) ofoutput tank 14 as follows:

$\begin{matrix}{R_{cas} = {\frac{Z_{l} + r_{o5}}{1 + {g{m_{5}.r_{o5}}}}{r_{o3}}{r_{o4}.( {1 + {g{m_{4}.r_{o2}}}} )}}} & (9)\end{matrix}$

Considering the gate-source capacitance Cgs₁ of the first transistor M₁and the gate-to-source capacitance Cgs₂ of the second transistor M₂ andsubstituting Equation (9) in Equation (6), then Equation (7) gives theinput impedance Zin as follows:

$\begin{matrix}{{{Z_{in} = \lbrack {( {\frac{1}{{gm}_{1}}{\frac{1}{Cgs_{1}}}} ) \cdot ( \frac{1 - {{( {\frac{Z_{l} + r_{o5}}{1 + {g{m_{5}.r_{o5}}}}{r_{o3}}{r_{o4}.( {1 + {g{m_{4}.r_{o2}}}} )}} ).R}{l.g}m{1.g}m3}}{1 + {{gm}2( {\frac{Z_{l} + r_{o5}}{1 + {g{m_{5}.r_{o5}}}}{r_{o3}}{r_{o4}.( {1 + {g{m_{4}.r_{o2}}}} )}} )}} )} \rbrack}}\frac{1}{Cgs_{2}}} & (10)\end{matrix}$

From Equation (9), the input impedance Zin follows the impedance ofoutput tank 14, which means that the input impedance Zin resonates atvery close frequency to the center frequency of output tank 14(deviation is mainly because of Cgs₂ and Cgs₁), where at the resonancefrequency the input resistance is set to be equal to the resistance ofthe RF source resistance R_(s).

Simulation Results

The LNA 12 was implemented in 90 nm silicon-on-insulator technology witha supply voltage V_(DD) of 1.2 V for frequency range of 1.4 GHz to 2.7GHz. The first transistor M₁ is biased with very low current of 0.28 mA.The bias currents of the second transistor M₂ and the third transistorM₃ are about 11.4 mA and 0.3 mA, respectively. The current consumptionis in the level of a conventional narrow band LNA. About 20 femtofaradsof capacitance for an input pad at the first node N1 and 100 picohenriesof parasitic inductance for the fixed voltage node GND1 pad areconsidered. The LNA 12 is matched to 50Ω at both the first node N1(i.e., the input node) and the fifth node N5 (i.e., the output node).

A high gain of >20 dB can be reached using an inductance value of 2.5nanohenries with a quality factor of 12 for the tank inductor L_(l). Thereverse isolation is relatively high because of the cascodeconfiguration of the fourth transistor M₄ and the fifth transistor M₅,which also acts as a cascode device for the first transistor M₁. Thethird transistor M₃ also provides additional isolation. Small signalparameters for input matching, reverse isolation, gain, and outputmatching at 2 GHz are shown in FIGS. 5A to 5D.

To demonstrate self-tuning of input matching, the center frequency ofthe output tank 14 is tuned at three frequency points: 1.4 GHz, 2 GHz,and 2.7 GHz. As can be observed from FIG. 6 , the input matching isself-tuned along with tuning the center frequency of output tank 14(FIG. 3 ). The selectivity at input helps to attenuate out-of-bandcomponents to improve the linearity.

Very low noise figure of 0.51 dB to 0.81 dB is achieved within the 1.4GHz to 2.7 GHz frequency range, as shown in FIG. 7A. The noisecontribution of each of the first transistor M₁, the second transistorM₂, the third transistor M₃, the fourth transistor M₄, the fifthtransistor M₅, load resistor (R₁), and bias resistor (Rb) is given bythe following Table 1. As can be observed from Table 1, the noise of thefirst transistor M₁ is cancelled and the noise contribution of the firstresistor R₁ and the bias resistor R_(b1) is considerably reduced (5% oftotal noise) by using this disclosed gm boosting technique. Table 1 alsodemonstrates the effectiveness of the disclosed embodiments to reducenoise figure of the LNA 12, because without using gm boosting, the noisecontribution of load and bias resistors can be quite large andcomparable with noise of the first transistor M₁. The noise figure ismainly determined by the gm of the second transistor M₂.

TABLE 1 Noise contribution of devices Device Parameter NoiseContribution (V2) % of Total Input rn 4.183e−9 76.06 M2 id 8.061e−1014.66 Rb Thermal 1.424e−10 2.59 R1 Thermal 1.291e−10 2.35 M5 id6.120e−11 1.11 M3 id 2.801e−11 0.51 M1 id 2.632e−11 0.48

According to FIG. 7B, the LNA 12 is unconditionally stable over a widefrequency range, since the stability factor is larger than one andbecause of high reverse isolation provided by employing two cascodedevices.

The second-order and third-order input-referred interference points areshown in FIGS. 8A and 8B, respectively, for 2 GHz input power. The LNAgain is set to 20.4 dB, and an IIP3 of −6 dBm is achieved. Thesecond-order harmonic indicates cancellation effects at input power 25dBm (specially notched around −20 dBm input power). Therefore, IIP2value depends on the extraction point. Two extraction points of smallinput power (−30 dBm) and large input power (−15 dBm) give +5.5 dBm and+13.5 dBm for IIP2, respectively.

With reference to FIG. 9 , the concepts described above may beimplemented in various types of wireless communication devices or userelements 16, such as mobile terminals, smart watches, tablets,computers, navigation devices, access points, and the like that supportwireless communications, such as cellular, wireless local area network(WLAN), Bluetooth, and near-field communications. The user elements 16will generally include a control system 18, a baseband processor 20,transmit circuitry 22, receive circuitry 24 that includes the LNA 12(FIG. 3 and FIG. 4 ), antenna switching circuitry 26, multiple antennas28, and user interface circuitry 30. The receive circuitry 24 receivesradio frequency signals via the antennas 28 and through the antennaswitching circuitry 26 from one or more basestations. A low-noiseamplifier and a filter cooperate to amplify and remove broadbandinterference from the received signal for processing. Downconversion anddigitization circuitry (not shown) will then downconvert the filtered,received signal to an intermediate or baseband frequency signal, whichis then digitized into one or more digital streams.

The baseband processor 20 processes the digitized received signal toextract the information or data bits conveyed in the received signal.This processing typically comprises demodulation, decoding, and errorcorrection operations. The baseband processor 20 is generallyimplemented in one or more digital signal processors andapplication-specific integrated circuits.

For transmission, the baseband processor 20 receives digitized data,which may represent voice, data, or control information, from thecontrol system 18, which it encodes for transmission. The encoded datais output to the transmit circuitry 22, where it is used by a modulatorto modulate a carrier signal that is at a desired transmit frequency orfrequencies. A power amplifier will amplify the modulated carrier signalto a level appropriate for transmission and deliver the modulatedcarrier signal through the antenna switching circuitry 26 to theantennas 28. The antennas 28 and the replicated transmit circuitry 22and receive circuitry 24 may provide spatial diversity. Modulation andprocessing details will be understood by those skilled in the art.

It is contemplated that any of the foregoing aspects, and/or variousseparate aspects and features as described herein, may be combined foradditional advantage. Any of the various embodiments as disclosed hereinmay be combined with one or more other disclosed embodiments unlessindicated to the contrary herein.

Those skilled in the art will recognize improvements and modificationsto the preferred embodiments of the present disclosure. All suchimprovements and modifications are considered within the scope of theconcepts disclosed herein and the claims that follow.

What is claimed is:
 1. A low-noise amplifier comprising: a firsttransistor having a first current terminal coupled to a supply voltagerail through a load resistor and a second current terminal coupled to aninput node, wherein a bias resistor is coupled between the input nodeand a fixed voltage node; a second transistor having a third currentterminal coupled to an output feedback node and a fourth currentterminal coupled to the fixed voltage node; and a feedback capacitorcoupled between a gate of the first transistor and the output feedbacknode, wherein capacitance of the feedback capacitor is sized toeliminate the need for coupling an input impedance matching inductor tothe input node.
 2. The low-noise amplifier of claim 1 wherein the fixedvoltage node is ground.
 3. The low-noise amplifier of claim 1 wherein acapacitance value for the feedback capacitor is between 100 femtofaradsand 500 femtofarads.
 4. The low-noise amplifier of claim 1 wherein acapacitance value of the feedback capacitor is 250 femtofarads ±20%. 5.The low-noise amplifier of claim 1 wherein a capacitance value for thefeedback capacitor is 250 femtofarads ±10%.
 6. The low-noise amplifierof claim 1 further comprising a third transistor having a gate coupledto the first current terminal of the first transistor, a fifth currentterminal coupled to the feedback output node, and a sixth currentterminal coupled to the fixed voltage node.
 7. The low-noise amplifierof claim 6 wherein the gate of the third transistor is coupled to thefirst current terminal of the first transistor by way of a couplingcapacitor.
 8. The low-noise amplifier of claim 6 wherein the secondtransistor is coupled to the feedback output node through acascode-configured fourth transistor.
 9. The low-noise amplifier ofclaim 8 wherein the feedback output node is coupled to an output nodethrough a cascode-configured fifth transistor.
 10. The low-noiseamplifier of claim 1 wherein the noise factor contribution of the loadresistor and the bias resistor is less than 5% of total noise.
 11. Amethod of amplifying a low-noise signal using a low-noise amplifierhaving a first transistor having a first current terminal coupled to asupply rail through a load resistor and a second current terminalcoupled to an input node, a bias resistor coupled between the input nodeand a fixed voltage node, a second transistor having a third currentterminal coupled to an output feedback node and a fourth currentterminal coupled to the fixed voltage node, and a feedback capacitorbetween a gate of the first transistor and the output feedback node, themethod comprising: applying a signal to the input node without employingan input matching inductor at the input node; and amplifying the signalusing the first transistor and the second transistor, thereby generatingan amplified output signal at the output feedback node.
 12. The methodof amplifying the low-noise signal using the low-noise amplifier ofclaim 11 wherein the fixed voltage node is ground.
 13. The method ofamplifying the low-noise signal using the low-noise amplifier of claim11 wherein a capacitance value for the feedback capacitor is betweenfemtofarads and 500 femtofarads.
 14. The method of amplifying thelow-noise signal using the low-noise amplifier of claim 11 wherein acapacitance value of the feedback capacitor is 250 femtofarads ±20%. 15.The method of amplifying the low-noise signal using the low-noiseamplifier of claim 11 wherein a capacitance value for the feedbackcapacitor is 250 femtofarads ±10%.
 16. The method of amplifying thelow-noise signal using the low-noise amplifier of claim 11 furthercomprising a third transistor having a gate coupled to the first currentterminal of the first transistor, a fifth current terminal coupled tothe feedback output node, and a sixth current terminal coupled to thefixed voltage node.
 17. The method of amplifying the low-noise signalusing the low-noise amplifier of claim 16 wherein the gate of the thirdtransistor is coupled to the first current terminal of the firsttransistor by way of a coupling capacitor.
 18. The method of amplifyingthe low-noise signal using the low-noise amplifier of claim 16 whereinthe second transistor is coupled to the feedback output node through acascode-configured fourth transistor.
 19. The method of amplifying thelow-noise signal using the low-noise amplifier of claim 18 wherein thefeedback output node is coupled to an output node through acascode-configured fifth transistor.
 20. The method of amplifying thelow-noise signal using the low-noise amplifier of claim 11 wherein thenoise factor contribution of the load resistor and the bias resistor isless than 5% of the total noise.
 21. A wireless communication devicecomprising: receive circuitry configured to receive radio frequency (RF)signals, wherein the receive circuitry comprises a low-noise amplifier(LNA) configured to amplify the RF signals; a baseband processorconfigured to process a digitized version of the RF signals received bythe receive circuitry and to extract the information or data bitsconveyed in the received RF signals; and a low-noise amplifiercomprising: a first transistor having a first current terminal coupledto a supply voltage rail through a load resistor and a second currentterminal coupled to an input node, wherein a bias resistor is coupledbetween the input node and a fixed voltage node; a second transistorhaving a third current terminal coupled to an output feedback node and afourth current terminal coupled to the fixed voltage node; and afeedback capacitor coupled between a gate of the first transistor andthe output feedback node, wherein capacitance of the feedback capacitoris sized to eliminate the need for coupling an input impedance matchinginductor to the input node.
 22. The wireless communication device ofclaim 21 wherein the fixed voltage node is ground.
 23. The wirelesscommunication device of claim 21 wherein a capacitance value for thefeedback capacitor is between 100 femtofarads and 500 femtofarads. 24.The wireless communication device of claim 21 wherein a capacitancevalue of the feedback capacitor is 250 femtofarads ±20%.
 25. Thewireless communication device of claim 21 wherein a capacitance valuefor the feedback capacitor is 250 femtofarads ±10%.
 26. The wirelesscommunication device of claim 21 further comprising a third transistorhaving a gate coupled to the first current terminal of the firsttransistor, a fifth current terminal coupled to the feedback outputnode, and a sixth current terminal coupled to the fixed voltage node.27. The wireless communication device of claim 26 wherein the gate ofthe third transistor is coupled to the first current terminal of thefirst transistor by way of a coupling capacitor.
 28. The wirelesscommunication device claim 26 wherein the second transistor is coupledto the feedback output node through a cascode-configured fourthtransistor.
 29. The wireless communication device of claim 28 whereinthe feedback output node is coupled to an output node through acascode-configured fifth transistor.
 30. The wireless communicationdevice of claim 21 wherein the noise factor contribution of the loadresistor and the bias resistor is less than 5% of total noise.